The present invention relates to a structure and method of manufacture for a semiconductor device which is configured as a one or more PN junctions within a polycrystalline silicon layer formed upon a thermal oxidation insulating film which covers a surface of a semiconductor substrate.
Semiconductor devices are known in the art which are formed as PN junctions upon an insulating film that is formed over a semiconductor substrate, for example as described in Japanese patent laid-open No. 58-151051, and in U.S. Pat. No. 4,492,974. Since no parasitic action occurs within such a semiconductor device, a plurality of elements can readily be configured as a set of PN junctions which are connected in series, and such a device has a wide range of applicability. For example, such a device is suitable for use as a temperature sensing element which employs the diode forward voltage temperature characteristic.
FIGS. 1, 2 and 3 show a specific example of a prior art semiconductor device which is configured as a plurality of diodes connected in series. FIG. 1 shows a cross-sectional view, FIG. 2 a plan view, and FIG. 3 the electrical circuit of the device. Reference numeral 10 denotes a semiconductor substrate having an insulating film 11 formed on a main surface thereof. A layer of polycrystalline silicon 12, referred to in the following as a polycrystalline silicon "island", is formed upon a predetermined region of the insulating film 11. Regions of the polycrystalline silicon island 12 are selectively doped with phosphorus or boron by ion implantation, to form a plurality of successively adjacently positioned annular N.sup.+ regions 12a and P.sup.+ regions 12b, disposed in a mutually concentric fashion, in a successively alternating manner as shown. An oxide film 13 is formed over this polycrystalline silicon island 12, and a surface protection film 14 is then formed thereon. Lead-out apertures are then formed, and electrodes 15a and 15b are then formed to respectively contact the innermost one of the N.sup.+ regions 12a and the outermost one of the N.sup.+ regions 12a. This completes the manufacture of the semiconductor device.
However with such a semiconductor device, the current-carrying capacity of the PN junctions is determined by the maximum current density per unit length of a PN junction. Thus, the current-carrying capacity of the entire semiconductor device is determined by that of the PN junction which has the shortest junction length, i.e. the peripherally innermost PN junction. As a result, an increase in the current-carrying capacity of such a device can only be attained by increasing the length of this peripherally innermost PN junction. Hence, the length of the peripherally outermost PN junction must be increased accordingly, whereby the overall area which is occupied by the PN functions of the device may become excessively large, i.e. the efficiency of area utilization is low. Furthermore with such a prior art configuration, one of the P.sup.+ regions 12b is disposed at the peripherally inward side of each of the N.sup.+ regions 12a, i.e. regions of different conduction type are disposed closely adjacent. Similarly, there is an N.sup.+ region 12a disposed at the peripherally inward side of each P.sup.+ region 12b, and corner portions of the resultant P-N junctions are formed, at which there is a high concentration of current flow. As a result, the level of applied energy at which device destruction begins (i.e. where applied energy is defined as the product of voltage applied across the device and device current) is lowered due to the excessive concentration of current flow which occurs at each of these PN junction corner portions.